Scaleable CMOS Current-Mode Preamplifier Design for an Optical Receiver View Full Text


Ontology type: schema:ScholarlyArticle     


Article Info

DATE

1997-02

AUTHORS

Myunghee Lee, Olivier Vendier, Martin A. Brooke, Nan Marie Jokerst

ABSTRACT

We have designed a process-insensitive preamplifierfor an optical receiver, fabricated it in several different minimumfeature sizes of standard digital CMOS, and demonstrated designscaleability of this analog integrated circuit design. The sameamplifier was fabricated in a 1.2 µm and two different0.8 µm processes through the MOSIS foundry [1].The amplifier uses a multi-stage, low-gain-per-stage approach.It has a total of 5 identical cascaded stages. Each stage isessentially a current mirror with a current gain of 3. Threeof these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with anInGaAs MSM detector by using a thin-film epilayer device separationand bonding technology [2]. This quasi-monolithic front-end of anoptical receiver virtually eliminates the parasitics between thephotodetector and the silicon CMOS preamplifier. We have demonstratedspeed and power dissipation improvement as the minimum feature sizeof the transistors shrink. More... »

PAGES

133-144

References to SciGraph publications

  • 1993-07. CMOS LED driver and PIN receiver for fiber optical communication at 150 mbit/sec in ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
  • Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1023/a:1008217109255

    DOI

    http://dx.doi.org/10.1023/a:1008217109255

    DIMENSIONS

    https://app.dimensions.ai/details/publication/pub.1019081891


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