Compact circuits for combined AES encryption/decryption View Full Text


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Article Info

DATE

2019-04

AUTHORS

Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni

ABSTRACT

The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8-bit datapath. However, this is an encryption-only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper, we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and decryption (ENC/DEC) while keeping the hardware overhead as low as possible. We report two constructions of the AES circuit. The first is an 8-bit serialized implementation that provides the functionality of both encryption and decryption and occupies around 2605 GE with a latency of 226 cycles. This is a substantial improvement over the next smallest AES ENC/DEC circuit (Grain of Sand) by Feldhofer et al. which takes around 3400 gates but has a latency of over 1000 cycles for both the encryption and decryption cycles. In the second part, we optimize the above architecture to provide the dual encryption/decryption functionality in only 2227 GE and latency of 246/326 cycles for the encryption and decryption operations, respectively. We take advantage of clock gating techniques to achieve Shiftrow and Inverse Shiftrow operations in 3 cycles instead of 1. This helps us replace many of the scan flip-flops in the design with ordinary flip-flops. Furthermore, we take advantage of the fact that the Inverse Mixcolumn matrix in AES is the cube of the Forward Mixcolumn matrix. Thus by executing the Forward Mixcolumn operation three times over the state, one can achieve the functionality of Inverse Mixcolumn. This saves some more gate area as one is no longer required to have a combined implementation of the Forward and Inverse Mixcolumn circuit. More... »

PAGES

1-15

References to SciGraph publications

  • 2002. The Design of Rijndael, AES — The Advanced Encryption Standard in NONE
  • 2015. Highly Efficient $$GF(2^8)$$ G F ( 2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS -- CHES 2015
  • 2005. A Systematic Evaluation of Compact Hardware Implementations for the Rijndael S-Box in TOPICS IN CRYPTOLOGY – CT-RSA 2005
  • 2003. Very Compact FPGA Implementation of the AES Algorithm in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2003
  • 2001. A Compact Rijndael Hardware Architecture with S-Box Optimization in ADVANCES IN CRYPTOLOGY — ASIACRYPT 2001
  • 2011. Pushing the Limits: A Very Compact and a Threshold Implementation of AES in ADVANCES IN CRYPTOLOGY – EUROCRYPT 2011
  • 2012. PRINCE – A Low-Latency Block Cipher for Pervasive Computing Applications in ADVANCES IN CRYPTOLOGY – ASIACRYPT 2012
  • 2015. Midori: A Block Cipher for Low Energy in ADVANCES IN CRYPTOLOGY – ASIACRYPT 2015
  • 2011. Piccolo: An Ultra-Lightweight Blockcipher in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2011
  • 2013-04. Logic Minimization Techniques with Applications to Cryptology in JOURNAL OF CRYPTOLOGY
  • 2011. The LED Block Cipher in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2011
  • 2016. A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2016
  • 2005. A Very Compact S-Box for AES in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2005
  • 2003-02-17. 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2002
  • 2007. PRESENT: An Ultra-Lightweight Block Cipher in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2007
  • 2006. HIGHT: A New Block Cipher Suitable for Low-Resource Device in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2006
  • 2016. Exploring Energy Efficiency of Lightweight Block Ciphers in SELECTED AREAS IN CRYPTOGRAPHY – SAC 2015
  • 2012. KLEIN: A New Family of Lightweight Block Ciphers in RFID. SECURITY AND PRIVACY
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    http://scigraph.springernature.com/pub.10.1007/s13389-017-0176-3

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    http://dx.doi.org/10.1007/s13389-017-0176-3

    DIMENSIONS

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    29 schema:description The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8-bit datapath. However, this is an encryption-only core and unable to cater to block cipher modes like CBC and ELmD that require access to both the AES encryption and decryption modules. In this paper, we look to investigate whether the basic circuit of Moradi et al. can be tweaked to provide dual functionality of encryption and decryption (ENC/DEC) while keeping the hardware overhead as low as possible. We report two constructions of the AES circuit. The first is an 8-bit serialized implementation that provides the functionality of both encryption and decryption and occupies around 2605 GE with a latency of 226 cycles. This is a substantial improvement over the next smallest AES ENC/DEC circuit (Grain of Sand) by Feldhofer et al. which takes around 3400 gates but has a latency of over 1000 cycles for both the encryption and decryption cycles. In the second part, we optimize the above architecture to provide the dual encryption/decryption functionality in only 2227 GE and latency of 246/326 cycles for the encryption and decryption operations, respectively. We take advantage of clock gating techniques to achieve Shiftrow and Inverse Shiftrow operations in 3 cycles instead of 1. This helps us replace many of the scan flip-flops in the design with ordinary flip-flops. Furthermore, we take advantage of the fact that the Inverse Mixcolumn matrix in AES is the cube of the Forward Mixcolumn matrix. Thus by executing the Forward Mixcolumn operation three times over the state, one can achieve the functionality of Inverse Mixcolumn. This saves some more gate area as one is no longer required to have a combined implementation of the Forward and Inverse Mixcolumn circuit.
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