Variety enhancement of PUF responses using the locations of random outputting RS latches View Full Text


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Article Info

DATE

2013-11

AUTHORS

Dai Yamamoto, Kazuo Sakiyama, Mitsugu Iwamoto, Kazuo Ohta, Masahiko Takenaka, Kouichi Itoh

ABSTRACT

Physical Unclonable Functions (PUFs) are expected to represent an important solution for secure ID generation and authentication etc. In general, manufactured PUFs are considered to be more secure when the pattern of outputs (the variety of responses) is larger, i.e., the response bit length is longer (e.g., 192-bit response is more secure than 128-bit one). However, the actual bit length is reduced because some response bits are inconsistent (random) for repeated measurements, which are regarded as unnecessary for ID generation and discarded. Latch-based PUFs with RS latches, for example, generate ideally responses depending on binary values output from RS latches (0/1). However, some RS latches output random responses which are inconsistent and cannot be used for reliable ID generation, so the variety of responses becomes smaller than . In this paper, we propose a novel Latch-based PUF structure, which outputs larger variety of responses by utilizing location information of the RS latches outputting the random responses. Differently from random responses themselves, this location information is determined during a manufacturing process, so almost fixed once PUFs are manufactured. The proposed PUF generates responses by considering random responses as the third stable value: using ternary values (0/1/random). We estimate the variety of responses generated by the proposed PUFs. According to our experiment with 40 FPGAs, a Latch-based PUF with 128 RS latches can improve it from to , this being maximized when the 128 latches outputs 0s, 1s, or random outputs with equal probability. We also show the appropriate RS latch structure for satisfying this condition, and validate it using two kinds of different Xilinx FPGAs: Spartan-3E and Spartan-6. The average error rate of responses is only 5.3 % when the core voltage is changed within the rated voltage range of the FPGAs. Our proposed PUF using ternary values enhances dramatically the variety of responses while keeping the reliability. More... »

PAGES

197-211

References to SciGraph publications

  • 2009. Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2009
  • 2011. Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2011
  • 2010-10-12. Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions in TOWARDS HARDWARE-INTRINSIC SECURITY
  • 2010. The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS, CHES 2010
  • 2012. PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions (PUFs) Cast in Silicon in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2012
  • 2012. Soft Decision Error Correction for Compact Memory-Based PUFs Using a Single Enrollment in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2012
  • 2007. FPGA Intrinsic PUFs and Their Use for IP Protection in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2007
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    http://scigraph.springernature.com/pub.10.1007/s13389-012-0044-0

    DOI

    http://dx.doi.org/10.1007/s13389-012-0044-0

    DIMENSIONS

    https://app.dimensions.ai/details/publication/pub.1033371328


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