Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement View Full Text


Ontology type: schema:ScholarlyArticle     


Article Info

DATE

2014-06

AUTHORS

Ramzi Ayadi, Bouraoui Ouni, Abdellatif Mtibaa

ABSTRACT

In this paper, we present a novel temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the whole latency of the design. This aim can be reached by minimizing the latency of the graph and the reconfiguration time at the same time. Consequently, our algorithm starts by an existing temporal partitioning. The existing temporal partitioning is the result of a whole latency optimization algorithm. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest value of reconfiguration time. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the design latency compared with others famous approaches used in this field. More... »

PAGES

133-141

References to SciGraph publications

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/s12530-013-9082-9

DOI

http://dx.doi.org/10.1007/s12530-013-9082-9

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1052463085


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