Designing balanced wrapper chains in 3D SoC under constrained TSVs View Full Text


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Article Info

DATE

2021-05-25

AUTHORS

Sabyasachee Banerjee, Soumendu Ghorui, Subhashis Majumder

ABSTRACT

Three-dimensional integrated circuit (3D-IC) has emerged as a savior of failing Moore’s law, where reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this work, we propose a simulated annealing-based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) is also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were conducted on several ITC’02 SoC benchmark and the results when compared with a recent work which showed that our proposed approach recorded better test lengths in more than 90% cases with an average reduction of 6.42% in test length. Our algorithms also used less number of TSVs in approximately 90% of the cases with an average reduction of 23.82% in the number of TSVs, in comparable CPU time. More... »

PAGES

219-230

References to SciGraph publications

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/s11334-021-00402-w

DOI

http://dx.doi.org/10.1007/s11334-021-00402-w

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1138331527


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[
  {
    "@context": "https://springernature.github.io/scigraph/jsonld/sgcontext.json", 
    "about": [
      {
        "id": "http://purl.org/au-research/vocabulary/anzsrc-for/2008/08", 
        "inDefinedTermSet": "http://purl.org/au-research/vocabulary/anzsrc-for/2008/", 
        "name": "Information and Computing Sciences", 
        "type": "DefinedTerm"
      }, 
      {
        "id": "http://purl.org/au-research/vocabulary/anzsrc-for/2008/0801", 
        "inDefinedTermSet": "http://purl.org/au-research/vocabulary/anzsrc-for/2008/", 
        "name": "Artificial Intelligence and Image Processing", 
        "type": "DefinedTerm"
      }
    ], 
    "author": [
      {
        "affiliation": {
          "alternateName": "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India", 
          "id": "http://www.grid.ac/institutes/grid.440742.1", 
          "name": [
            "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India"
          ], 
          "type": "Organization"
        }, 
        "familyName": "Banerjee", 
        "givenName": "Sabyasachee", 
        "id": "sg:person.013114255053.05", 
        "sameAs": [
          "https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.013114255053.05"
        ], 
        "type": "Person"
      }, 
      {
        "affiliation": {
          "alternateName": "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India", 
          "id": "http://www.grid.ac/institutes/grid.440742.1", 
          "name": [
            "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India"
          ], 
          "type": "Organization"
        }, 
        "familyName": "Ghorui", 
        "givenName": "Soumendu", 
        "id": "sg:person.012004764451.51", 
        "sameAs": [
          "https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.012004764451.51"
        ], 
        "type": "Person"
      }, 
      {
        "affiliation": {
          "alternateName": "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India", 
          "id": "http://www.grid.ac/institutes/grid.440742.1", 
          "name": [
            "Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India"
          ], 
          "type": "Organization"
        }, 
        "familyName": "Majumder", 
        "givenName": "Subhashis", 
        "id": "sg:person.012677256771.36", 
        "sameAs": [
          "https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.012677256771.36"
        ], 
        "type": "Person"
      }
    ], 
    "citation": [
      {
        "id": "sg:pub.10.1007/s11390-013-1316-6", 
        "sameAs": [
          "https://app.dimensions.ai/details/publication/pub.1017313496", 
          "https://doi.org/10.1007/s11390-013-1316-6"
        ], 
        "type": "CreativeWork"
      }, 
      {
        "id": "sg:pub.10.1007/0-387-34609-0", 
        "sameAs": [
          "https://app.dimensions.ai/details/publication/pub.1042467291", 
          "https://doi.org/10.1007/0-387-34609-0"
        ], 
        "type": "CreativeWork"
      }, 
      {
        "id": "sg:pub.10.1007/s10836-020-05872-7", 
        "sameAs": [
          "https://app.dimensions.ai/details/publication/pub.1126273774", 
          "https://doi.org/10.1007/s10836-020-05872-7"
        ], 
        "type": "CreativeWork"
      }, 
      {
        "id": "sg:pub.10.1007/s10836-016-5638-5", 
        "sameAs": [
          "https://app.dimensions.ai/details/publication/pub.1074248021", 
          "https://doi.org/10.1007/s10836-016-5638-5"
        ], 
        "type": "CreativeWork"
      }, 
      {
        "id": "sg:pub.10.1023/a:1014916913577", 
        "sameAs": [
          "https://app.dimensions.ai/details/publication/pub.1036944021", 
          "https://doi.org/10.1023/a:1014916913577"
        ], 
        "type": "CreativeWork"
      }
    ], 
    "datePublished": "2021-05-25", 
    "datePublishedReg": "2021-05-25", 
    "description": "Three-dimensional integrated circuit (3D-IC) has emerged as a savior of failing Moore\u2019s law, where reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this work, we propose a simulated annealing-based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) is also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were conducted on several ITC\u201902 SoC benchmark and the results when compared with a recent work which showed that our proposed approach recorded better test lengths in more than 90% cases with an average reduction of 6.42% in test length. Our algorithms also used less number of TSVs in approximately 90% of the cases with an average reduction of 23.82% in the number of TSVs, in comparable CPU time.", 
    "genre": "article", 
    "id": "sg:pub.10.1007/s11334-021-00402-w", 
    "inLanguage": "en", 
    "isAccessibleForFree": false, 
    "isPartOf": [
      {
        "id": "sg:journal.1044675", 
        "issn": [
          "1614-5046", 
          "1614-5054"
        ], 
        "name": "Innovations in Systems and Software Engineering", 
        "publisher": "Springer Nature", 
        "type": "Periodical"
      }, 
      {
        "issueNumber": "3", 
        "type": "PublicationIssue"
      }, 
      {
        "type": "PublicationVolume", 
        "volumeNumber": "17"
      }
    ], 
    "keywords": [
      "comparable CPU time", 
      "number of TSVs", 
      "length of interconnect", 
      "wrapper chains", 
      "CPU time", 
      "design algorithm", 
      "SoC benchmarks", 
      "algorithm", 
      "test length", 
      "high computation", 
      "less number", 
      "law", 
      "Moore's law", 
      "recent work", 
      "computation", 
      "complex SoCs", 
      "constraints", 
      "rigorous experiments", 
      "number", 
      "TSV", 
      "benchmarks", 
      "cases", 
      "length", 
      "work", 
      "chain", 
      "approach", 
      "circuit", 
      "interconnects", 
      "advantages", 
      "time", 
      "experiments", 
      "core", 
      "results", 
      "integration", 
      "average reduction", 
      "heterogeneous integration", 
      "less time", 
      "SOC", 
      "reduction", 
      "volume", 
      "challenges", 
      "benefits", 
      "savior", 
      "large complex SoCs", 
      "annealing-based wrapper chain design algorithm", 
      "wrapper chain design algorithm", 
      "chain design algorithm", 
      "ITC\u201902 SoC benchmark", 
      "better test lengths", 
      "balanced wrapper chains"
    ], 
    "name": "Designing balanced wrapper chains in 3D SoC under constrained TSVs", 
    "pagination": "219-230", 
    "productId": [
      {
        "name": "dimensions_id", 
        "type": "PropertyValue", 
        "value": [
          "pub.1138331527"
        ]
      }, 
      {
        "name": "doi", 
        "type": "PropertyValue", 
        "value": [
          "10.1007/s11334-021-00402-w"
        ]
      }
    ], 
    "sameAs": [
      "https://doi.org/10.1007/s11334-021-00402-w", 
      "https://app.dimensions.ai/details/publication/pub.1138331527"
    ], 
    "sdDataset": "articles", 
    "sdDatePublished": "2022-01-01T19:00", 
    "sdLicense": "https://scigraph.springernature.com/explorer/license/", 
    "sdPublisher": {
      "name": "Springer Nature - SN SciGraph project", 
      "type": "Organization"
    }, 
    "sdSource": "s3://com-springernature-scigraph/baseset/20220101/entities/gbq_results/article/article_877.jsonl", 
    "type": "ScholarlyArticle", 
    "url": "https://doi.org/10.1007/s11334-021-00402-w"
  }
]
 

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This table displays all metadata directly associated to this object as RDF triples.

142 TRIPLES      22 PREDICATES      80 URIs      67 LITERALS      6 BLANK NODES

Subject Predicate Object
1 sg:pub.10.1007/s11334-021-00402-w schema:about anzsrc-for:08
2 anzsrc-for:0801
3 schema:author Nb0828e04b6bb4735955440436aca0a45
4 schema:citation sg:pub.10.1007/0-387-34609-0
5 sg:pub.10.1007/s10836-016-5638-5
6 sg:pub.10.1007/s10836-020-05872-7
7 sg:pub.10.1007/s11390-013-1316-6
8 sg:pub.10.1023/a:1014916913577
9 schema:datePublished 2021-05-25
10 schema:datePublishedReg 2021-05-25
11 schema:description Three-dimensional integrated circuit (3D-IC) has emerged as a savior of failing Moore’s law, where reduced length of interconnects is guaranteed with some added advantages like heterogeneous integration, higher computation per volume, etc. These benefits are also exhibited in 3D SoCs (3D System on Chips) to use the already built cores. However, testing these large complex SoCs in lesser time has become a challenge. In this work, we propose a simulated annealing-based wrapper chain design algorithm that will balance the length of the wrapper chain. The number of TSVs (Through Silicon Vias) is also kept as a constraint so that the number of TSVs could also be reduced. Rigorous experiments were conducted on several ITC’02 SoC benchmark and the results when compared with a recent work which showed that our proposed approach recorded better test lengths in more than 90% cases with an average reduction of 6.42% in test length. Our algorithms also used less number of TSVs in approximately 90% of the cases with an average reduction of 23.82% in the number of TSVs, in comparable CPU time.
12 schema:genre article
13 schema:inLanguage en
14 schema:isAccessibleForFree false
15 schema:isPartOf N5dfb384ba73849e7a5d55446c6d31690
16 Nf65f034d47e647daab1359e6cf664e1e
17 sg:journal.1044675
18 schema:keywords CPU time
19 ITC’02 SoC benchmark
20 Moore's law
21 SOC
22 SoC benchmarks
23 TSV
24 advantages
25 algorithm
26 annealing-based wrapper chain design algorithm
27 approach
28 average reduction
29 balanced wrapper chains
30 benchmarks
31 benefits
32 better test lengths
33 cases
34 chain
35 chain design algorithm
36 challenges
37 circuit
38 comparable CPU time
39 complex SoCs
40 computation
41 constraints
42 core
43 design algorithm
44 experiments
45 heterogeneous integration
46 high computation
47 integration
48 interconnects
49 large complex SoCs
50 law
51 length
52 length of interconnect
53 less number
54 less time
55 number
56 number of TSVs
57 recent work
58 reduction
59 results
60 rigorous experiments
61 savior
62 test length
63 time
64 volume
65 work
66 wrapper chain design algorithm
67 wrapper chains
68 schema:name Designing balanced wrapper chains in 3D SoC under constrained TSVs
69 schema:pagination 219-230
70 schema:productId N1e431992314e4c6a81359ec57dc3fb96
71 Ne50dbe91c0cd42ad867a27871f944660
72 schema:sameAs https://app.dimensions.ai/details/publication/pub.1138331527
73 https://doi.org/10.1007/s11334-021-00402-w
74 schema:sdDatePublished 2022-01-01T19:00
75 schema:sdLicense https://scigraph.springernature.com/explorer/license/
76 schema:sdPublisher Nfc80de3e855f42ffae39fea916b2137b
77 schema:url https://doi.org/10.1007/s11334-021-00402-w
78 sgo:license sg:explorer/license/
79 sgo:sdDataset articles
80 rdf:type schema:ScholarlyArticle
81 N1e431992314e4c6a81359ec57dc3fb96 schema:name dimensions_id
82 schema:value pub.1138331527
83 rdf:type schema:PropertyValue
84 N5dfb384ba73849e7a5d55446c6d31690 schema:volumeNumber 17
85 rdf:type schema:PublicationVolume
86 N7e3bbb6221c54b049fd0eb603ec5b6d4 rdf:first sg:person.012677256771.36
87 rdf:rest rdf:nil
88 Nb0828e04b6bb4735955440436aca0a45 rdf:first sg:person.013114255053.05
89 rdf:rest Neba75a82df72424b97ae7e1a0f6af19b
90 Ne50dbe91c0cd42ad867a27871f944660 schema:name doi
91 schema:value 10.1007/s11334-021-00402-w
92 rdf:type schema:PropertyValue
93 Neba75a82df72424b97ae7e1a0f6af19b rdf:first sg:person.012004764451.51
94 rdf:rest N7e3bbb6221c54b049fd0eb603ec5b6d4
95 Nf65f034d47e647daab1359e6cf664e1e schema:issueNumber 3
96 rdf:type schema:PublicationIssue
97 Nfc80de3e855f42ffae39fea916b2137b schema:name Springer Nature - SN SciGraph project
98 rdf:type schema:Organization
99 anzsrc-for:08 schema:inDefinedTermSet anzsrc-for:
100 schema:name Information and Computing Sciences
101 rdf:type schema:DefinedTerm
102 anzsrc-for:0801 schema:inDefinedTermSet anzsrc-for:
103 schema:name Artificial Intelligence and Image Processing
104 rdf:type schema:DefinedTerm
105 sg:journal.1044675 schema:issn 1614-5046
106 1614-5054
107 schema:name Innovations in Systems and Software Engineering
108 schema:publisher Springer Nature
109 rdf:type schema:Periodical
110 sg:person.012004764451.51 schema:affiliation grid-institutes:grid.440742.1
111 schema:familyName Ghorui
112 schema:givenName Soumendu
113 schema:sameAs https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.012004764451.51
114 rdf:type schema:Person
115 sg:person.012677256771.36 schema:affiliation grid-institutes:grid.440742.1
116 schema:familyName Majumder
117 schema:givenName Subhashis
118 schema:sameAs https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.012677256771.36
119 rdf:type schema:Person
120 sg:person.013114255053.05 schema:affiliation grid-institutes:grid.440742.1
121 schema:familyName Banerjee
122 schema:givenName Sabyasachee
123 schema:sameAs https://app.dimensions.ai/discover/publication?and_facet_researcher=ur.013114255053.05
124 rdf:type schema:Person
125 sg:pub.10.1007/0-387-34609-0 schema:sameAs https://app.dimensions.ai/details/publication/pub.1042467291
126 https://doi.org/10.1007/0-387-34609-0
127 rdf:type schema:CreativeWork
128 sg:pub.10.1007/s10836-016-5638-5 schema:sameAs https://app.dimensions.ai/details/publication/pub.1074248021
129 https://doi.org/10.1007/s10836-016-5638-5
130 rdf:type schema:CreativeWork
131 sg:pub.10.1007/s10836-020-05872-7 schema:sameAs https://app.dimensions.ai/details/publication/pub.1126273774
132 https://doi.org/10.1007/s10836-020-05872-7
133 rdf:type schema:CreativeWork
134 sg:pub.10.1007/s11390-013-1316-6 schema:sameAs https://app.dimensions.ai/details/publication/pub.1017313496
135 https://doi.org/10.1007/s11390-013-1316-6
136 rdf:type schema:CreativeWork
137 sg:pub.10.1023/a:1014916913577 schema:sameAs https://app.dimensions.ai/details/publication/pub.1036944021
138 https://doi.org/10.1023/a:1014916913577
139 rdf:type schema:CreativeWork
140 grid-institutes:grid.440742.1 schema:alternateName Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India
141 schema:name Department of Computer Science and Engineering, Heritage Institute of Technology, 700107, Kolkata, West Bengal, India
142 rdf:type schema:Organization
 




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