An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking View Full Text


Ontology type: schema:ScholarlyArticle     


Article Info

DATE

2012-01

AUTHORS

Ching-Te Chiu, Yu-Hao Hsu, Jen-Ming Wu, Shuo-Hung Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Yar-Sun Hsu

ABSTRACT

In this paper, we propose a reconfigurable load balanced symmetric TDM switch fabric. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 3.65 mm × 3.57 mm prototype switch fabric IC, including a digital 8 × 8 switch core, eight 16B20B CODECs, eight SERDES ports, eight CML I/O interfaces and a PLL, in 0.18 μm CMOS technology. The digital 8 × 8 switch core has reconfigurable connection patterns for the ease of scaling up to an N×N switch (N is power of 4). We propose the 16B20B CODEC scheme to reduce the switch core clock rate by half. In the SERDES, we employ the half-rate scheme and then use static CMOS gates for the low power consumption. We develop a low power, area-efficient and wide-band CML I/O interface with our patented PMOS active load inductive-peaking scheme for high-speed data transmission. With the 16B20B CODEC, the half-rate, and the PMOS active load schemes, almost 50% of the power is saved as compared with the design of the 8B10B CODEC, the full-rate and on-chip inductors CML schemes. Our measurement shows that an 8 × 8 switch fabric IC can achieve 20 Gbps switching rate and consumes only about 690 mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs. More... »

PAGES

57-73

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/s11265-010-0518-1

DOI

http://dx.doi.org/10.1007/s11265-010-0518-1

DIMENSIONS

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