Energy efficient processing of motion estimation for embedded multimedia systems View Full Text


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Article Info

DATE

2017-04-01

AUTHORS

Jooheung Lee

ABSTRACT

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions. More... »

PAGES

24749-24765

References to SciGraph publications

  • 2008-01-08. A real-time motion estimation FPGA architecture in JOURNAL OF REAL-TIME IMAGE PROCESSING
  • 2007-05-22. Adaptive Motion Estimation Processor for Autonomous Video Devices in EURASIP JOURNAL ON EMBEDDED SYSTEMS
  • Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1007/s11042-017-4645-6

    DOI

    http://dx.doi.org/10.1007/s11042-017-4645-6

    DIMENSIONS

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