Ontology type: schema:ScholarlyArticle
2014-12
AUTHORSTakayuki Okazawa, Ippei Akita, Makoto Ishida
ABSTRACTThis paper presents a self-calibrating dynamic latched comparator that does not require additional static current or load capacitors to reduce its offset voltage. The proposed comparator uses a reconfigurable differential pair at the input stage; the configuration is determined by a digital calibration scheme that automatically matches the differential pair, resulting in a low offset voltage. We present a novel time-domain offset detection technique in the calibration loop, which is based on measuring the metastable time of the comparator. The offset detector uses a ring time-to-digital converter with a simple time amplifier. The proposed comparator was fabricated with standard 180 nm CMOS technology; it achieves a standard deviation of 1.3 mV offset voltage and 13.5μW power consumption with a power supply of 1.5 V. More... »
PAGES561-570
http://scigraph.springernature.com/pub.10.1007/s10470-014-0410-1
DOIhttp://dx.doi.org/10.1007/s10470-014-0410-1
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