Volker
Schindler
Information and Computing Sciences
reasons
FastMM
728-743
multiplication
path
parallel
RSAa crypto chip
features
crypto chip
1996
encryption
logic
pure MM data path
computation speed
conditions
https://doi.org/10.1007/978-3-642-80350-5_62
design
high computation speed
influence
high-speed data path
behavior
https://scigraph.springernature.com/explorer/license/
mechanism influence
multiplication algorithm
en
1996-01-01
loading
special features
RSA encryption
RSAα crypto chip
cryptographic algorithms
control logic
chapter
operation frequency
chapters
true
High speed devices for public key cryptography are of emerging interest. For this reason, the RSAa crypto chip was designed. It is an architecture capable of performing fast RSA encryption and other cryptographic algorithms based on modulo multiplication. Besides the modulo multiplication algorithm called FastMM, the reasons for its high computation speed are the As Parallel As Possible APAP architecture, as well as the high operation frequency. The RSAα crypto chip also contains on-chip RAM and a special-purpose control logic, enabling special features like encrypted key loading. However, this control mechanism influences to some extend testability of the MM data path which is the heart of the chip. For this reason, the RSAβ crypto chip has been designed to be able to evaluate the behaviour of the pure MM data path. In the following, we describe the strategies used with the RSAβ crypto chip for testing the MM data path under realistical conditions. In this context, analyzing control signal flow turns out to be the key action.
public key cryptography
RSAβ crypto chip
modulo multiplication
high speed devices
key loading
data path
speed
control signal flow
chip
flow
extend testability
signal flow
frequency
devices
chip RAM
Possible APAP architecture
testability
key cryptography
APAP architecture
control mechanism influences
following
speed devices
interest
high operation frequency
rams
key actions
Testing a High-Speed Data Path The Design of the RSAβ Crypto Chip
strategies
realistical conditions
heart
fast RSA encryption
architecture
MM data path
special-purpose control logic
action
2021-11-01T18:55
algorithm
modulo multiplication algorithm
cryptography
context
Springer Nature
978-3-642-80352-9
J.UCS The Journal of Universal Computer Science
978-3-642-80350-5
Computation Theory and Mathematics
Karl C.
Posch
doi
10.1007/978-3-642-80350-5_62
Calude
Cristian
Maurer
Hermann
dimensions_id
pub.1044671704
Wolfgang
Mayerwieser
Salomaa
Arto
Graz University of Technology, Austria
Graz University of Technology, Austria
Reinhard
Posch
Springer Nature - SN SciGraph project