Testing a High-Speed Data Path The Design of the RSAβ Crypto Chip View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

1996

AUTHORS

Wolfgang Mayerwieser , Karl C. Posch , Reinhard Posch , Volker Schindler

ABSTRACT

High speed devices for public key cryptography are of emerging interest. For this reason, the RSAa crypto chip was designed. It is an architecture capable of performing fast RSA encryption and other cryptographic algorithms based on modulo multiplication. Besides the modulo multiplication algorithm called FastMM, the reasons for its high computation speed are the As Parallel As Possible APAP architecture, as well as the high operation frequency. The RSAα crypto chip also contains on-chip RAM and a special-purpose control logic, enabling special features like encrypted key loading. However, this control mechanism influences to some extend testability of the MM data path which is the heart of the chip. For this reason, the RSAβ crypto chip has been designed to be able to evaluate the behaviour of the pure MM data path. In the following, we describe the strategies used with the RSAβ crypto chip for testing the MM data path under realistical conditions. In this context, analyzing control signal flow turns out to be the key action. More... »

PAGES

728-743

Book

TITLE

J.UCS The Journal of Universal Computer Science

ISBN

978-3-642-80352-9
978-3-642-80350-5

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-642-80350-5_62

DOI

http://dx.doi.org/10.1007/978-3-642-80350-5_62

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1044671704


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