Ontology type: schema:Chapter Open Access: True
2011
AUTHORS ABSTRACTMulti-precision multiplication is one of the most fundamental operations on microprocessors to allow public-key cryptography such as RSA and Elliptic Curve Cryptography (ECC). In this paper, we present a novel multiplication technique that increases the performance of multiplication by sophisticated caching of operands. Our method significantly reduces the number of needed load instructions which is usually one of the most expensive operation on modern processors. We evaluate our new technique on an 8-bit ATmega128 microcontroller and compare the result with existing solutions. Our implementation needs only 2,395 clock cycles for a 160-bit multiplication which outperforms related work by a factor of 10% to 23%. The number of required load instructions is reduced from 167 (needed for the best known hybrid multiplication) to only 80. Our implementation scales very well even for larger Integer sizes (required for RSA) and limited register sets. It further fully complies to existing multiply-accumulate instructions that are integrated in most of the available processors. More... »
PAGES459-474
Cryptographic Hardware and Embedded Systems – CHES 2011
ISBN
978-3-642-23950-2
978-3-642-23951-9
http://scigraph.springernature.com/pub.10.1007/978-3-642-23951-9_30
DOIhttp://dx.doi.org/10.1007/978-3-642-23951-9_30
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