Faster and Timing-Attack Resistant AES-GCM View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2009

AUTHORS

Emilia Käsper , Peter Schwabe

ABSTRACT

We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous implementations, while simultaneously offering protection against timing attacks. In particular, it is the only cache-timing-attack resistant implementation offering competitive speeds for stream as well as for packet encryption: for 576-byte packets, we improve performance over previous bitsliced implementations by more than a factor of 2. We also report more than 30% improved speeds for lookup-table based Galois/Counter mode authentication, achieving 10.68 cycles/byte for authenticated encryption. Furthermore, we present the first constant-time implementation of AES-GCM that has a reasonable speed of 21.99 cycles/byte, thus offering a full suite of timing-analysis resistant software for authenticated encryption. More... »

PAGES

1-17

References to SciGraph publications

Book

TITLE

Cryptographic Hardware and Embedded Systems - CHES 2009

ISBN

978-3-642-04137-2
978-3-642-04138-9

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-642-04138-9_1

DOI

http://dx.doi.org/10.1007/978-3-642-04138-9_1

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1038763693


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