New AES Software Speed Records View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2008

AUTHORS

Daniel J. Bernstein , Peter Schwabe

ABSTRACT

This paper presents new speed records for AES software, taking advantage of (1) architecture-dependent reduction of instructions used to compute AES and (2) microarchitecture-dependent reduction of cycles used for those instructions. A wide variety of common CPU architectures—amd64, ppc32, sparcv9, and x86—are discussed in detail, along with several specific microarchitectures.

PAGES

322-336

References to SciGraph publications

  • 2007. AES Encryption Implementation and Analysis on Commodity Graphics Processing Units in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2007
  • 2008. A Fast and Cache-Timing Resistant Implementation of the AES in TOPICS IN CRYPTOLOGY – CT-RSA 2008
  • 2006. Bitslice Implementation of AES in CRYPTOLOGY AND NETWORK SECURITY
  • 2006. AES Software Implementations on ARM7TDMI in PROGRESS IN CRYPTOLOGY - INDOCRYPT 2006
  • 2007. On the Power of Bitslice Implementation on Intel Core2 Processor in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2007
  • 2005. How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4 Processors in FAST SOFTWARE ENCRYPTION
  • 2003-02-17. Efficient Software Implementation of AES on 32-Bit Platforms in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2002
  • 2006. How Far Can We Go on the x64 Processors? in FAST SOFTWARE ENCRYPTION
  • 2006. Cache Attacks and Countermeasures: The Case of AES in TOPICS IN CRYPTOLOGY – CT-RSA 2006
  • Book

    TITLE

    Progress in Cryptology - INDOCRYPT 2008

    ISBN

    978-3-540-89753-8
    978-3-540-89754-5

    Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1007/978-3-540-89754-5_25

    DOI

    http://dx.doi.org/10.1007/978-3-540-89754-5_25

    DIMENSIONS

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