Boosting AES Performance on a Tiny Processor Core View Full Text


Ontology type: schema:Chapter     


Chapter Info

DATE

2008

AUTHORS

Stefan Tillich , Christoph Herbst

ABSTRACT

Notwithstanding the tremendous increase in performance of desktop computers, more and more computational work is performed on small embedded microprocessors. Particularly, tiny 8-bit microcontrollers are being employed in many different application settings ranging from cars over everyday appliances like doorlock systems or room climate controls to complex distributed setups like wireless sensor networks. In order to provide security for these applications, cryptographic algorithms need to be implemented on these microcontrollers. While efficient implementation is a general optimization goal, tiny embedded systems normally have further demands for low energy consumption, small code size, low RAM usage and possibly also short latency. In this work we propose a small enhancement for 8-bit Advanced Virtual RISC (AVR) cores, which improves the situation for all of these demands for implementations of the Advanced Encryption Standard. Particularly, a single 128-bit block can be encrypted or decrypted in under 1,300 clock cycles. Compared to a fast software implementation, this constitutes an increase of performance by a factor of up to 3.6. The hardware cost for the proposed extensions is limited to about 1.1 kGates. More... »

PAGES

170-186

References to SciGraph publications

  • 2006. Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box in EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION
  • 2002. The Design of Rijndael, AES — The Advanced Encryption Standard in NONE
  • 2006. Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2006
  • 2005. A Very Compact S-Box for AES in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2005
  • 2007. Power Analysis Resistant AES Implementation with Instruction Set Extensions in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2007
  • 2007. VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors in ARITHMETIC OF FINITE FIELDS
  • 2004. Cryptonite – A Programmable Crypto Processor Architecture for High-Bandwidth Applications in ORGANIC AND PERVASIVE COMPUTING – ARCS 2004
  • Book

    TITLE

    Topics in Cryptology – CT-RSA 2008

    ISBN

    978-3-540-79262-8
    978-3-540-79263-5

    Author Affiliations

    Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1007/978-3-540-79263-5_11

    DOI

    http://dx.doi.org/10.1007/978-3-540-79263-5_11

    DIMENSIONS

    https://app.dimensions.ai/details/publication/pub.1016217574


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