Instruction Buffering Exploration for Low Energy Embedded Processors View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2003

AUTHORS

Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Henk Corporaal , Francky Catthoor

ABSTRACT

For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. Especially software controlled loop buffers are energy efficient. However current compilers do not fully take advantage of the possibilities of such loop buffers. This paper presents an algorithm the explore for an application or a set of applications what is the optimal loop buffer configuration and the optimal way to use this configuration. Results for the MediaBench application suite show an additional 35% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional approaches to the loop buffer without any performance implications. More... »

PAGES

409-419

References to SciGraph publications

  • 2002. A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors in INTEGRATED CIRCUIT DESIGN. POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
  • 2002. Data Access and Storage Management for Embedded Programmable Processors in NONE
  • Book

    TITLE

    Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

    ISBN

    978-3-540-20074-1
    978-3-540-39762-5

    Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1007/978-3-540-39762-5_47

    DOI

    http://dx.doi.org/10.1007/978-3-540-39762-5_47

    DIMENSIONS

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