Instruction Set Architectures for Quantum Processing Units View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2017-10-20

AUTHORS

Keith A. Britt , Travis S. Humble

ABSTRACT

Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows. We briefly describe several prominent quantum computational models, their associated quantum processing units (QPUs), and the adoption of these devices as accelerators within high-performance computing systems. Emphasizing the interface to the QPU, we analyze instruction set architectures based on reduced and complex instruction sets, i.e., RISC and CISC architectures. We clarify the role of conventional constraints on memory addressing and instruction widths within the quantum computing context. Finally, we examine existing quantum computing platforms, including the D-Wave 2000Q and IBM Quantum Experience, within the context of future ISA development and HPC needs. More... »

PAGES

98-105

Book

TITLE

High Performance Computing

ISBN

978-3-319-67629-6
978-3-319-67630-2

Author Affiliations

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-319-67630-2_8

DOI

http://dx.doi.org/10.1007/978-3-319-67630-2_8

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1092291372


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