Reverse Product-Scanning Multiplication and Squaring on 8-Bit AVR Processors View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2015

AUTHORS

Zhe Liu , Hwajeong Seo , Johann Großschädl , Howon Kim

ABSTRACT

High performance, small code size, and good scalability are important requirements for software implementations of multi-precision arithmetic algorithms to fit resource-limited embedded systems. In this paper, we describe optimization techniques to speed up multi-precision multiplication and squaring on the AVR ATmega series of 8-bit microcontrollers. First, we present a new approach to perform multi-precision multiplication, called Reverse Product Scanning (RPS), that resembles the hybrid technique of Gura et al., but calculates the byte-products in the inner loop in reverse order. The RPS method processes four bytes of the two operands in each iteration of the inner loop and employs two carry-catcher registers to minimize the number of add instructions. We also describe an optimized algorithm for multi-precision squaring based on the RPS technique that is, depending on the operand length, up to 44.3 % faster than multiplication. Our AVR Assembly implementations of RPS multiplication and RPS squaring occupy less than 1 kB of code space each and are written in a parameterized fashion so that they can support operands of varying length without recompilation. Despite this high level of flexibility, our RPS multiplication outperforms the looped variant of Hutter et al.’s operand-caching technique and saves between 40 and 51 % of code size. We also combine our RPS multiplication and squaring routines with Karatsuba’s method to further reduce execution time. When executed on an ATmega128 processor, the “karatsubarized RPS method” needs only 85 k clock cycles for a 1024-bit multiplication (or 48 k cycles for a squaring). These results show that it is possible to achieve high performance without sacrificing code size or scalability. More... »

PAGES

158-175

References to SciGraph publications

  • 2005. Energy-Efficient Software Implementation of Long Integer Modular Arithmetic in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2005
  • 2004. Instruction Set Extensions for Fast Arithmetic in Finite Fields GF(p) and GF(2m) in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2004
  • 2015-09. Multiprecision multiplication on AVR revisited in JOURNAL OF CRYPTOGRAPHIC ENGINEERING
  • 2011. Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS – CHES 2011
  • 2013. Multi-precision Squaring for Public-Key Cryptography on Embedded Microprocessors in PROGRESS IN CRYPTOLOGY – INDOCRYPT 2013
  • 2012. Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors in INFORMATION SECURITY APPLICATIONS
  • 2007. Enabling Full-Size Public-Key Algorithms on 8-Bit Sensor Nodes in SECURITY AND PRIVACY IN AD-HOC AND SENSOR NETWORKS
  • 2004. Comparing Elliptic Curve Cryptography and RSA on 8-bit CPUs in CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2004
  • 2014. New Speed Records for Montgomery Modular Multiplication on 8-Bit AVR Microcontrollers in PROGRESS IN CRYPTOLOGY – AFRICACRYPT 2014
  • 2009. Batch Binary Edwards in ADVANCES IN CRYPTOLOGY - CRYPTO 2009
  • Book

    TITLE

    Information and Communications Security

    ISBN

    978-3-319-21965-3
    978-3-319-21966-0

    Identifiers

    URI

    http://scigraph.springernature.com/pub.10.1007/978-3-319-21966-0_12

    DOI

    http://dx.doi.org/10.1007/978-3-319-21966-0_12

    DIMENSIONS

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