Tofu Interconnect 2: System-on-Chip Integration of High-Performance Interconnect View Full Text


Ontology type: schema:Chapter     


Chapter Info

DATE

2014

AUTHORS

Yuichiro Ajima , Tomohiro Inoue , Shinya Hiramoto , Shunji Uno , Shinji Sumimoto , Kenichi Miura , Naoyuki Shida , Takahiro Kawashima , Takayuki Okamoto , Osamu Moriyama , Yoshiro Ikeda , Takekazu Tabata , Takahide Yoshikawa , Ken Seki , Toshiyuki Shimizu

ABSTRACT

The Tofu Interconnect 2 (Tofu2) is a system interconnect designed for the Fujitsu’s next generation successor to the PRIMEHPC FX10 supercomputer. Tofu2 inherited the 6-dimensional mesh/torus network topology from its predecessor, and it increases the link throughput by two and half times. It is integrated into a newly developed SPARC64TM processor chip and takes advantages of system-on-chip implementation by removing off-chip I/O between a processor chip and an interconnect controller. Tofu2 also introduces new features such as the atomic read-modify-write communication functions, the session-mode control queue for the offloading of collective communications, and harmless cache injection technique to reduce communication latency. More... »

PAGES

498-507

Book

TITLE

Supercomputing

ISBN

978-3-319-07517-4
978-3-319-07518-1

Author Affiliations

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-319-07518-1_35

DOI

http://dx.doi.org/10.1007/978-3-319-07518-1_35

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1048786217


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