Analysis of Novel Stress Enhancement Effect Based on Damascene Gate Process with eSiGe S/D for pFETs View Full Text


Ontology type: schema:Chapter     


Chapter Info

DATE

2007

AUTHORS

S. Yamakawa , J. Wang , Y. Tateshita , K. Nagano , M. Tsukamoto , H. Ohri , N. Nagashima , H. Ansai

ABSTRACT

A novel stress enhancement effect based on the damascene gate process with embedded SiGe (eSiGe) S/D for pFET is analyzed in detail, using stress simulation and Ion measurement, for the first time. Removal of a dummy poly-Si gate eliminates the repulsive force from the gate with a resulting enhancement of lateral compressive stress from eSiGe S/D. The stress enhancement effect is proved by device fabrication and measurement. Furthermore, a new channel recess process is proposed and investigated. Channel recess further increases stress at the channel. This effect is also confirmed by measurement, resulting in 14% current enhancement. More... »

PAGES

109-112

Book

TITLE

Simulation of Semiconductor Processes and Devices 2007

ISBN

978-3-211-72860-4

Author Affiliations

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-211-72861-1_26

DOI

http://dx.doi.org/10.1007/978-3-211-72861-1_26

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1015819679


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