Efficient Set-Bit Driven Shift-Add Binary Multiplier View Full Text


Ontology type: schema:Chapter     


Chapter Info

DATE

2018-11-02

AUTHORS

Alvernon Walker , Evelyn Sowells-Boone

ABSTRACT

A binary shift-add multiplier with a variable multiplication completion time that ranges from 1 to n clock cycles, where n is the number of bits in the input operands, is presented. The number of cycles required for this multiplier equals the number of bits that are set in one of the input operands except when it equals zero in that case it is one. The multiplier architecture and control logic are presented in this paper. Circuit simulation results are also reported. More... »

PAGES

1346-1350

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-3-030-01177-2_99

DOI

http://dx.doi.org/10.1007/978-3-030-01177-2_99

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1107966413


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