Robustness-Agile Encryptor for ATM Networks View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2000

AUTHORS

Herbert Leitold , Wolfgang Mayerwieser , Udo Payer , Karl Christian Posch , Reinhard Posch , Johannes Wolkerstorfer

ABSTRACT

This paper describes a robustness-agile ATM encryption unit which exploits parallel control processes. A VLSI chip implementing these concepts is presented. This single-chip encryptor performs CBC-mode Triple-DES encryption up to 155 Mbps with delays well below one ATM cell period. The microchip advances the field of confidentiality services in ATM networks in several dimensions: First, the delay introduced due to encryption has been minimized and is negligible in terms of Quality of Services requirements of delay sensitive applications. Second, outer-CBC Triple-DES is supported at 155 Mbps, so far not used by ATM encryptors. Third, the unit is scalable in the number of virtual connections, i.e. the number of agile session keys. Finally, the single-chip approach allows to integrate encryption into the end-user ATM access device, such as a desktop PC. More... »

PAGES

231-240

Book

TITLE

Information Security for Global Information Infrastructures

ISBN

978-1-4757-5479-7
978-0-387-35515-3

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/978-0-387-35515-3_24

DOI

http://dx.doi.org/10.1007/978-0-387-35515-3_24

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1039456091


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