A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors View Full Text


Ontology type: schema:Chapter      Open Access: True


Chapter Info

DATE

2002

AUTHORS

Murali Jayapala , Francisco Barat , Pieter Op de Beeck , Francky Catthoor , Geert Deconinck , Henk Corporaal

ABSTRACT

In the current embedded processors for media applications, up to 30% of the total processor power is consumed in the instruction memory hierarchy. In this context, we present an inherently low energy clustered instruction memory hierarchy template. Small instruction memories are distributed over groups of functional units and the interconnects are localized in order to minimize energy consumption. Furthermore, we present a simple profile based algorithm to optimally synthesize the L0 clusters, for a given application. Using a few representative multimedia benchmarks we show that up to 45% of the L0 buffer energy can be reduced using our clustering approach. More... »

PAGES

258-267

Book

TITLE

Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

ISBN

978-3-540-44143-4
978-3-540-45716-9

Identifiers

URI

http://scigraph.springernature.com/pub.10.1007/3-540-45716-x_26

DOI

http://dx.doi.org/10.1007/3-540-45716-x_26

DIMENSIONS

https://app.dimensions.ai/details/publication/pub.1015617311


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