Mary Jane Irwin


Ontology type: schema:Person     


Person Info

NAME

Mary Jane

SURNAME

Irwin

Publications in SciGraph latest 50 shown

  • 2010-11-19 Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs in NANOELECTRONIC CIRCUIT DESIGN
  • 2010-02 Total Power Optimization for Combinational Logic Using Genetic Algorithms in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 2009 In-Network Caching for Chip Multiprocessors in HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS
  • 2009 Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors in HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS
  • 2008-11 Thermal neutron induced soft error rate measurement in semiconductor memories and circuits in JOURNAL OF RADIOANALYTICAL AND NUCLEAR CHEMISTRY
  • 2007-10 Reliability-aware Co-synthesis for Embedded Systems in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 2006 Effect of Power Optimizations on Soft Error Rate in VLSI-SOC: FROM SYSTEMS TO CHIPS
  • 2006 Characterizing the Performance and Energy Attributes of Scientific Simulations in COMPUTATIONAL SCIENCE – ICCS 2006
  • 2004-05 Instruction Scheduling for Low Power in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 2004-03 Optimizing Leakage Energy Consumption in Cache Bitlines in DESIGN AUTOMATION FOR EMBEDDED SYSTEMS
  • 2004 A Dual-VDD Low Power FPGA Architecture in FIELD PROGRAMMABLE LOGIC AND APPLICATION
  • 2004 Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations in ULTRA LOW-POWER ELECTRONICS AND DESIGN
  • 2004 Using Data Compression to Increase Energy Savings in Multi-bank Memories in EURO-PAR 2004 PARALLEL PROCESSING
  • 2004 Exploring the Possibility of Operating in the Compressed Domain in EURO-PAR 2004 PARALLEL PROCESSING
  • 2003 Address Register Assignment for Reducing Code Size in COMPILER CONSTRUCTION
  • 2002-11 Energy-performance trade-offs for spatial access methods on memory-resident data in THE VLDB JOURNAL
  • 2002 Tools and Techniques for Integrated Hardware-Software Energy Optimizations in POWER AWARE DESIGN METHODOLOGIES
  • 2002 Compiler Optimizations for Low Power Systems in POWER AWARE COMPUTING
  • 2001 Characterization of Memory Energy Behavior in WORKLOAD CHARACTERIZATION OF EMERGING COMPUTER APPLICATIONS
  • 2001 Experimental Evaluation of Energy Behavior of Iteration Space Tiling in LANGUAGES AND COMPILERS FOR PARALLEL COMPUTING
  • 2001 Towards Energy-Aware Iteration Space Tiling in LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS
  • 2000 A Holistic Approach to System Level Energy Optimization in INTEGRATED CIRCUIT DESIGN
  • 2000 Energy-Aware Instruction Scheduling in HIGH PERFORMANCE COMPUTING — HIPC 2000
  • 1999-08 Aggressive Dynamic Execution of Decoded Traces in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1998-07 A Parallel ASIC Architecture for Efficient Fractal Image Coding in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1996-08 An optimal time multiplication free algorithm for edge detection on a mesh in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1995-04 Digit pipelined arithmetic on fine-grain array processors in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1993-12 Intermediate-level vision tasks on a memory array architecture in MACHINE VISION AND APPLICATIONS
  • 1991-05 Image processing on a memory array architecture in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1990-04 A case for digit serial VLSI signal processors in JOURNAL OF SIGNAL PROCESSING SYSTEMS
  • 1987-03 Digit pipelined processors in THE JOURNAL OF SUPERCOMPUTING
  • Affiliations

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