A Tile-Based Processor Architecture Model For High Efficiency Embedded Homogneous Multicore Platforms


Ontology type: sgo:Patent     


Patent Info

DATE

2011-08-04T00:00

AUTHORS

MANET, PHILIPPE , ROUSSEAU, BERTRAND

ABSTRACT

The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables. More... »

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