Memory array architecture with two-terminal memory cells


Ontology type: sgo:Patent     


Patent Info

DATE

N/A

AUTHORS

Hagop Nazarian , Sung Hyun Jo , Wei Lu

ABSTRACT

A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor. More... »

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