Field programmable gate array utilizing two-terminal non-volatile memory


Ontology type: sgo:Patent     


Patent Info

DATE

2018-08-21T00:00

AUTHORS

Mehdi Asnaashari , Hagop Nazarian , Sang Nguyen

ABSTRACT

A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal. More... »

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